The present invention generally relates to metal oxide semiconductor field effect transistors (MOSFETs) and, more particularly, to a novel MOSFET with a new source/drain structure exhibiting low junction leakage and low junction capacitance.
The feature sizes of integrated circuit (IC) complementary metal oxide semiconductor (CMOS) devices continue to shrink. This reduction in size requires careful engineering of the source and drain structures of CMOS devices. In particular, what is needed is a shallower junction, lower parasitic resistance and lower junction capacitance.
It is therefore an object of the present invention to provide a novel MOSFET having a new source/drain structure and methods for making the same.
According to the invention, there is provided a novel MOSFET structure with a new source/drain (S/D) structure. The S/D conductors are located on the shallow trench isolation (STI) to achieve low junction leakage and low junction capacitance. The S/D junction depth is defined by an STI etch step (according to a first method of making the invention) or a silicon etch step (according to a second method of making the invention). By controlling the etch depth, a very shallow junction depth is achieved. There is a low variation of gate length, since the gate area is defined by etching crystal silicon, not by etching polycrystalline silicon. There is a low aspect ratio between the gate and the S/D, since the gate conductor and the source and drain conductors are aligned on same level. In other words, the gate conductor, and the source and drain conductors are arranged in substantially the same plane. As used herein, the term xe2x80x9caspect ratioxe2x80x9d is understood to mean the ratio of the depth to the width of a trench in the semiconductor substrate. A silicide technique is applied to the source and drain for low parasitic resistance; however, this will not result in severe S/D junction leakage, since the source and drain conductors sit on the STI.